IP Cores are widely used in FPGA development to incorporate proven functionality in a design.

They reduce development time and increase design quality, especially in complex designs. The IP Cores from Allied Vision Schongau for the GigE Vision, USB3 Vision and CoaXPress transport layers and the SubLVDS and MIPI-CSI2 sensor interfaces are designed to support customers in building their own vision components.

A typical device design consists of several functional blocks as well as IP Cores from the FPGA vendor. The architecture may be complex, requiring from the developer a good knowledge of the FPGA and firmware. To facilitate the integration of Allied Vision Schongau’s IP Cores, it is our philosophy to provide a fully functioning reference design for an evaluation platform as similar as possible to the target platform. These reference designs help speed up integration and reduce development costs.